Voltage unbalance and short circuits in distribution networks adversely affect the performance of gridtied voltage source inverters (VSIs). Consequently, the dc-link voltage ripple may significantly increase leading to operation of VSI in an unsatisfactory manner. Conventionally in order to maintain the negative sequence current under unbalanced conditions, low-pass/trap filter in the current control loop are required which significantly reduce the controller bandwidth. In order to minimize the dc-link voltage ripple without impairing the controller bandwidth, this paper investigates the design and performance of Proportional–Integral–Resonant (PIR) controller in improving the performance of the VSI under unbalanced condition. The proposed design methodology is validated through simulations and experimental results
