Quantum-dot Cellular Automata (QCA) is a new nanoscale computing architecture that has ultra-low power, high device density, and possible applicability to future nano-communication systems. In this paper, we present optimized QCA-based even parity generator and parity checker circuits with efficient XOR logic. The proposed designs reduce area and cell count significantly while maintaining stable logical operation. The circuits were drawn and simulated in QCADesigner-E and analyzed using QCAPro for energy dissipation and polarization error. Results show that the proposed parity generator reduces 57% cell count and 20% area over existing designs, whereas the parity checker reduces 67% cell count and 12.5% area. These improvements indicate the potential of the proposed circuits for low-power and small-area error detection mechanisms in nanoscale communication systems.
