The article delves into QCA technology's potential for low-power, low-latency computation, highlighting the importance of XOR gates in full-adder circuits. It introduces an efficient QCA circuit, focusing on an approximate full-adder with single-layer XOR logic. This design, with a latency of 0.5 clock phases, an area of 0.02 µm², and utilizing only 12 cells, outperforms previous ones in speed and occupies a smaller area.
